To meet the ever-increasing demands with respect to device and circuit performance, circuit designers have proposed new device architectures. One technique to improve performance of a circuit, for example of a CMOS device, is to fabricate the circuit on a so-called silicon-on-insulator (SOI) substrate, as illustrated in FIG. 1. An SOI substrate comprises an insulating layer 101 formed on a bulk substrate 103, for example, a silicon substrate. The insulating layer is generally formed of silicon dioxide and is sometimes referred to as a buried oxide layer (BOX) layer. Bulk substrate 103 is typically P-doped. An active silicon layer 105 is formed on the insulating layer. Active regions 107 for a field effect transistor device, defined by shallow trench isolation structures 109, are formed in active silicon layer 105. For an N-MOS transistor, the active regions 107 (the source and drain of the transistor) are N-doped and the region 111 between active regions 107 is P-doped. Further, a gate electrode 113, formed on a gate insulation layer 115, is formed on region 111 of active silicon layer 105. The resulting transistor is entirely electrically isolated from the regions surrounding the transistor area.
Gate insulation layers 115 having a high dielectric constant (“high-k”), e.g., having a dielectric constant of about 25 or greater, and metal gate electrodes 113 improve the performance of complementary metal-oxide semiconductor (“CMOS”) transistors. High-k gate dielectrics are desirable in small feature size technologies since conventional gate dielectrics, such as silicon dioxide, are too thin and they result in high tunneling current, as well as other problems. Further, metal gate electrodes improve NFET and PFET transistor performance over polysilicon gate electrodes by having a low resistance and by not causing undesirable depletion of carriers at the interface between gate dielectric 115 and channel 111.
Integration of the new device elements to enhance device performance make the integration flow increasingly complicated, resulting in increased costs and new sources of yield degradation. In particular the high-K/metal gate incorporation in the gate electrode not only impacts the downstream processing, but also gets impacted by it. Hence it is important to completely encapsulate the gate electrode using spacers prior to further processing. The spacer scheme has to be compatible with the metal gate as well as with epitaxially grown silicon germanium (eSiGe) integration (and/or silicon carbon) for the source and drain regions and device centering.
A typical gate first integration of the high-K/metal gate electrode involves four main spacers to achieve eSiGe integration and device centering. As illustrated in FIG. 2A, BOX layer 201 and active silicon layer 203 are formed on bulk substrate 205. Shallow trench isolation region 207 is formed in active silicon layer 203 isolating PFET 209 from NFET 211. High-K/metal gate 213, amorphous silicon layer 215, and nitride cap 217 are formed on active silicon layer 203 for PFET 209 and for NFET 211. A first spacer 219 is formed on each side of high-K/metal gate 213, amorphous silicon layer 215, and nitride cap 217. First spacer 219 is a non-oxide spacer to encapsulate the high-K/metal gate electrode 213. A second spacer 221, an oxide spacer which is typically low temperature oxide (LTO) using tetraethyl orthosilicate (TEOS) and ozone as precursors, is formed on first non-oxide spacer 219.
Adverting to FIG. 2B, a nitride layer 223 is formed over silicon layer 203, PFET 209, and NFET 211. The nitride layer is then etched from the top surface of PFET 209 and from active silicon layer 203 near PFET 209, leaving third spacer 225 on second spacer 221, as illustrated in FIG. 2C. Nitride layer 223 remains on NFET 211 as a protection layer for subsequent source and drain formation for PFET 209. The formation of third spacer 225 “pulls down” the first spacers 219 and second spacers 221, as indicated at 227 in FIG. 2D.
Cavities, defined by third spacers 225, are etched in active silicon layer 203, and silicon germanium (SiGe) is epitaxially grown in the cavities to form source and drain regions 229 for PFET 209, as illustrated in FIG. 2D. After the source and drain regions 229 are formed, third spacers 225, the remaining nitride layer 223, and nitride caps 217 are removed by wet etching, typically using hot phosphoric acid. Adverting to FIG. 2E, it has been found that during removal of the nitride, second LTO spacer 221 is also partially etched. The wet etching causes a change in the dimension of the second LTO spacer 221 that is not controlled. Hence, for reliable centering of the devices (i.e., for controlling the distances from the channel of the device for subsequent implants), the second LTO spacer 221 must be stripped and a new fourth LTO spacer must be formed. However, stripping of the second LTO spacer 221, not only adds extra manufacturing steps, but also causes thinning of first non-oxide spacer 219, thereby decreasing protection of the metal gate.
A need therefore exists for methodology enabling the fabrication of semiconductor devices comprising second spacers that are substantially resistant to nitride etching, such that they need not be removed and replaced and for the resulting improved semiconductor devices having improved protection of the metal gate and improved reliability.